This is the Linux app named Rocket Chip whose latest release can be downloaded as RocketChipv1.6sourcecode.tar.gz. It can be run online in the free hosting provider OnWorks for workstations.
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Rocket Chip
DESCRIPTION
Rocket Chip is a generator for RISC-V based System-on-Chip (SoC) designs, developed originally at UC Berkeley and now maintained via the Chips Alliance. Using Chisel (a hardware construction language embedded in Scala), Rocket Chip lets users parameterize and configure RISC-V cores (Rocket core, BOOM etc), memory subsystems, buses, caches, accelerators, tile interconnects etc. It supports simulation, FPGA prototyping, RTL generation, and synthesis for hardware fabrication.
Features
- SoC generator using parameterizable RISC-V cores (Rocket in-order, optionally BOOM out-of-order etc)
- Support for configurable cache hierarchies, memory subsystems, tiles, coherent interconnects etc
- Simulations via Verilator, support for unit-level and cycle-accurate simulations etc
- Capability to target FPGA for prototyping boards as well as producing RTL for ASIC flows
- Use of modern toolchains / build tools: Chisel, Scala, Nix for build environment, integration with IDEs like IntelliJ/VSCode etc
- Parameterization allows customizing everything like number of cores, accelerators, tile layout, clock domain etc to match different requirements (power, performance, area)
Programming Language
Scala
Categories
This is an application that can also be fetched from https://sourceforge.net/projects/rocket-chip.mirror/. It has been hosted in OnWorks in order to be run online in an easiest way from one of our free Operative Systems.
